**Job Title**
Senior ASIC Design Manager
**About Us**
- At Cognichip, we are building the next-generation AI-enabled solutions to empower semiconductor design engineers with a 10x productivity boost through specialized generative models, agentic workflows, and seamless integration with high-performance EDA engines.
**Role Overview**
- We are seeking a Senior ASIC Manager to lead a high-performing engineering team at the intersection of silicon design and artificial intelligence. In this role, you will bridge the gap between deep hardware expertise and cutting-edge AI, managing a team focused on re-imagining chip design flows with an AI-first mindset.
- You will be responsible for charting the path to incorporate enterprise silicon know-how into intelligent systems for AI-native, production-quality chip design and verification, while directly mentoring engineers and scaling our Toronto footprint.
**Key Responsibilities**
**Team Leadership & Growth:**
- Lead, mentor, and scale a highly technical team of ASIC design and verification engineers.
- Foster a collaborative environment where deep silicon expertise meets cutting-edge AI research.
**Innovation & Bottleneck Resolution:**
- Guide the team in identifying bottlenecks in advanced chip design processes and devising AI models, tools, and workflows to drastically improve engineering outcomes.
**Execution & Delivery:**
- Define execution and delivery, ensuring project milestones are met with production-quality execution.
**Required Qualifications**
- Experience: 15+ years of experience in a mix of individual contributor roles and leading highly technical teams.
- Proven Management Track Record: Demonstrated experience managing engineering teams, executing performance reviews, and steering technical roadmaps.
- Silicon Expertise: Extensive hands-on experience in Digital IC, ASIC, or SoC design, with strong proficiency in SystemVerilog RTL and STA.
- Microarchitecture: Solid understanding of advanced concepts including pipelines, FIFOs, DMA engines, caches, and on-chip interconnects, networking.
- Full-Cycle Familiarity: Deep familiarity with the full design cycle (lint, CDC/RDC, functional simulation, and STA) and the ability to guide engineers through complex RTL design tradeoffs.
- Software Literacy: Proficiency in Python and experience integrating EDA tools into automated workflows.
- Local Presence: Must be located in or willing to relocate to the Greater Toronto Area.
**Preferred Qualifications**
- AI/ML Exposure: Demonstrated experience with AI/ML systems, prompt engineering, context engineering, or managing teams working on AI-assisted tool flows.
- Community Engagement: Contributions to open-source chip design, EDA tooling, or AI/ML infrastructure.
**What We Offer**
- A foundational leadership role shaping how AI transforms the semiconductor industry.
- A collaborative environment combining deep hardware expertise with generative AI innovation.
- Competitive compensation, equity, and comprehensive benefits.
- We are an equal opportunity employer committed to building a diverse and inclusive team.
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